Akeana CEO Presents Keynote Digital India RISC-V (DIR-V) 2025
Rabin Sugumar, Akeana’s Co-Founder and CEO delivers a keynote at Digital India RISC-V (DIR-V) 2025. Akeana has developed a design where there is a basic pipeline skeleton over which all these features are layered as configurable options. This allows Akeana to create small microcontroller cores as well as a few orders of magnitude larger data center/mobile cores from a single database as a continuum.
Interview with Akeana: RISC-V Summit Europe 2025
Interview with RISC-V CEO, Andrea Gallo and Akeana’s Head of Product, Graham Wilson at the RISC-V Summit in Europe, 2025.
Breaking Performance Barriers: RISC-V Summit 2025
Presentation given by Graham Wilson at the RISC-V Summit in Europe, 2025. Learn how Akeana enables next generation SoC with leading edge performance. This performance comes from CPU compute capability, single and multi-threaded, along with performance scalability of multi-core and multi-cluster systems.
Introducing Akeana Video
Elevating RISC-V to World Class Performance Levels! Akeana is unique as a RISC-V IP vendor in providing the highest quality IP for processors, system IP, and advanced multi-core interconnect systems. Our world class solution leverages the popular RISC-V architecture by providing performance cores, with rich feature sets, for the widest range of market implementations possible.