Demonstrations Shown at the RISC-V Summit, Santa Clara 2025
For higher performance, better system management/resource utilization and lower latency data processing, Multi-Threading (SMT) processors are needed for next generation SoCs. The webinar goes through what SMT is and highlight use cases/applications that greatly benefit from SMT.
Streamlining High Performance RISC-V IP Development with Cadence’s Verification Solution
Dive into Akeana’s verification methodology developed around Cadence’s ecosystem, showcasing how the combination of these tools enabled rapid design cycle optimization.
Accelerating RISC-V Processor Development with Palladium Cloud
This presentation describes how Palladium Cloud is used to emulate various RISC-V workloads and interface protocols so DV team can quickly identify and resolve system-level and performance bugs that can only be traced at system-level and with real-world workloads.
Simultaneous Multi-Threading: Needed for Accelerated Heterogenous Compute and Low-Latency Data Processing
Advanced SoC architectures for leading edge applications such as Automotive, Edge AI (ex: Robotics), Datacentre have evolved to Heterogenous compute systems to provide the highest end compute with the best possible power efficiency. For higher performance, better system management/resource utilization and lower latency data processing, Multi-Threading (SMT) processors are needed for next generation SoCs. The webinar goes through what SMT is and highlight use cases/applications that greatly benefit from SMT.