This is a demonstration of the Akeana 1200 RISC-V processor (RV64 In-Order core) showing Simultaneous Multi-Threading running 1, 2 and 4 threads. This demonstration was shown at the RISC-V Summit Santa Clara 2025, at the Akeana booth.

This is a demonstration of the Akeana 5100 RISC-V processor (RV64 Out-of-Order core) showing Simultaneous Multi-Threading running 1, 2 and 4 threads. This demonstration was shown at the RISC-V Summit Santa Clara 2025, at the Akeana booth.

This is the compilation of the 4 demonstrations shown at the RISC-V Summit Santa Clara 2025 within the Akeana Booth.

This is a demonstration of the Akeana Data Movement Engine, implemented from our RV64 In-Order core with Simultaneous Multi-Threading technology. This demonstration was shown at the RISC-V Summit Santa Clara 2025, in the Akaena booth.

This video shows the Akeana 5100 core enabled with Hypervisor running Linux OS various applications, on a Synopsys HAPS-100 emulation platform.

This video shows a demonstration of the Akeana 1200 AI core with 2048-bit Vector extension, AI acceleration instructions, running on the Cadence Palladium emulation platform.