Akeana 5000 Series

A line of 64-bit, RISC-V, ultra-high performance processors

Akeana 5000 Series
Processors

The Akeana 5000 Series of processors is highly configurable and customizable, supporting applications such as mobile computation, data center, and cloud networking. The Akeana 5000 Series is optimized to give industry-leading performance, is capable of supporting rich-OS (e.g. Android, Linux) application computation, and has the ability to scale to hundreds of coherent processors.

These processors can be configured with support for 1-, 2-, or 4-way Multi-threading.

The Akeana 5000 Series represents the high range of Akeana’s three processor product lines , offering customers one of the broadest processor IP portfolios. Start your journey today with one or more of these Akeana processors.

12-stage pipeline, Out-of-Order architecture
MMU with
2048-entry,
8-way TLB
Multi-threaded architecture support
6-wide to 10-wide issue architecture supported

Akeana 5000 Series Processor Diagram

Akeana 5000 Series
Standard Configurations

Basic 5000 Series ConfigurationProductStandard FeaturesTypical Applications
RV64GCVBK_Zicbo + USH instruction set
Full RVA23 RISC-V Profile
Single and Double-Precision Floating-Point
User Mode
Supervisor Mode
Hypervisor extension
Vector extension (128 bits)
Vector Crypto extension
12-stage, out-of-order pipeline
48 bits Virtual Address range
256K L2 cache
Scalable to fully-coherent many-core clusters
ECC support
AXI/ACE (512 bits)
Physical Memory Protection (PMP) with 16 entries
MMU
Akeana 51004-way instruction dispatch
L1 I-cache: 32 KB/core
L1 D-cache: 32KB/core
33 bits Physical Address Space
MMU with 512-entry, 4-way TLB

"Big" core in Big/Little configurations
with Akeana 1000 Series Little cores

Akeana 52006-way instruction dispatch
L1 I-cache: 32 KB/core
L1 D-cache: 32 KB/core
L2 cache prefetcher
39 bits Physical Address Space
MMU with 1024-entry, 4-way TLB

“Big” core in Big/Little configurations
with Akeana 1000 Series Little cores;
Laptop core


Akeana 53008-way instruction dispatch
L1 I-cache: 64 KB/core
L1 D-cache: 64 KB/core
L2 cache prefetcher
39 bits Physical Address Space
MMU with 2048-entry, 8-way TLB

Datacenter / Infrastructure compute core

Add-On Options Include

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