Videos

11/05/25

Demonstrations Shown at the RISC-V Summit, Santa Clara 2025

For higher performance, better system management/resource utilization and lower latency data processing, Multi-Threading (SMT) processors are needed for next generation SoCs. The webinar goes through what SMT is and highlight use cases/applications that greatly benefit from SMT.
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08/12/25

Streamlining High Performance RISC-V IP Development with Cadence’s Verification Solution

Dive into Akeana's verification methodology developed around Cadence's ecosystem, showcasing how the combination of these tools enabled rapid design cycle optimization.
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08/12/25

Accelerating RISC-V Processor Development with Palladium Cloud

This presentation describes how Palladium Cloud is used to emulate various RISC-V workloads and interface protocols so DV team can quickly identify and resolve system-level and performance bugs that can only be traced at system-level and with real-world workloads.
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07/30/25

Simultaneous Multi-Threading: Needed for Accelerated Heterogenous Compute and Low-Latency Data Processing

Advanced SoC architectures for leading edge applications such as Automotive, Edge AI (ex: Robotics), Datacentre have evolved to Heterogenous compute systems to provide the highest end compute with the best possible power efficiency. For higher performance, better system management/resource utilization and lower latency data processing, Multi-Threading (SMT) processors are needed for next generation SoCs. The webinar goes through what SMT is and highlight use cases/applications that greatly benefit from SMT.
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05/31/25

Akeana CEO Presents Keynote Digital India RISC-V (DIR-V) 2025

Rabin Sugumar, Akeana's Co-Founder and CEO delivers a keynote at Digital India RISC-V (DIR-V) 2025. Akeana has developed a design where there is a basic pipeline skeleton over which all these features are layered as configurable options. This allows Akeana to create small microcontroller cores as well as a few orders of magnitude larger data center/mobile cores from a single database as a continuum.
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06/20/25

Interview with Akeana: RISC-V Summit Europe 2025

Interview with RISC-V CEO, Andrea Gallo and Akeana’s Head of Product, Graham Wilson at the RISC-V Summit in Europe, 2025.
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06/01/25

Breaking Performance Barriers: RISC-V Summit 2025

Presentation given by Graham Wilson at the RISC-V Summit in Europe, 2025. Learn how Akeana enables next generation SoC with leading edge performance. This performance comes from CPU compute capability, single and multi-threaded, along with performance scalability of multi-core and multi-cluster systems.
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02/11/25

Introducing Akeana Video

Elevating RISC-V to World Class Performance Levels! Akeana is unique as a RISC-V IP vendor in providing the highest quality IP for processors, system IP, and advanced multi-core interconnect systems. Our world class solution leverages the popular RISC-V architecture by providing performance cores, with rich feature sets,
for the widest range of market implementations possible.
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02/06/25

Webinar on Leveraging RISC-V as a Unified Heterogeneous HW & SW Platform

Today’s SoC developers need flexibility in computing systems and interconnect schemes that allow them to meet compute/watt requirements and the needs of CPU-xPU AI systems. In this webinar, learn how Akeana is enabling SoC developers to use RISC-V-based solutions for next-generation AI chips.
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10/31/24

Presentation on Breaking RISC-V Performance Barriers: RISC-V Summit Santa Clara 2024

Keynote at the RISC-V North America Summit by Graham Wilson, Head of Product at Akeana, introducing the RISC-V Processor IP company, which has recently come out of stealth mode. This keynote will go through the company, range of IP products available and benefits offered to customers.
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