Akeana tapes out highest performance RVA23 Alpine test chip
The tape out of Alpine in December 2025 marks a major milestone for Akeana and the RISC-V ecosystem. Built in 4nm, Alpine is the highest-performance RVA23-compatible server-class test chip and software development platform to date.
Breaking the Compute Bottleneck: Power, Memory, and the New AI Architecture Paradigms
One problem is that current AI systems devote all their resources to even the simplest questions, noted Rabin Sugumar, co-founder and CEO of Akeana. “A lot of solutions tend to be brute force,” he said. “If you ask ChatGPT, ‘Where do I go for coffee?’ All 600 billion parameters are fetched, and the whole compute goes through.”
proteanTecs and Akeana Announce Joint Initiative to Drive Next-Generation RISC-V Processor Performance
proteanTecs® and Akeana today announced their collaboration to deliver a joint solution for RISC-V processors that enhances power and performance, speeds product ramp and improves in-field reliability for next-generation devices.
Demonstrations Shown at the RISC-V Summit, Santa Clara 2025
For higher performance, better system management/resource utilization and lower latency data processing, Multi-Threading (SMT) processors are needed for next generation SoCs. The webinar goes through what SMT is and highlight use cases/applications that greatly benefit from SMT.